IBIS Macromodel Task Group

Meeting date: 30 September 2008

Members (asterisk for those attending):
  Ambrish Varma, Cadence Design Systems
* Anders Ekholm, Ericsson
* Arpad Muranyi, Mentor Graphics Corp.
  Barry Katz, SiSoft
* Bob Ross, Teraspeed Consulting Group
  Brad Brim, Sigrity
  Brad Griffin, Cadence Design Systems
* David Banas, Xilinx
  Donald Telian, consultant
  Doug White, Cisco Systems
  Essaid Bensoudane, ST Microelectronics
  Fangyi Rao, Agilent
  Ganesh Narayanaswamy, ST Micro
  Gang Kang, Sigrity
  Hemant Shah, Cadence Design Systems
  Ian Dodd, Agilent
  Joe Abler, IBM
* John Angulo, Mentor Graphics
  John Shields, Mentor Graphics
  Ken Willis, Cadence Design Systems
  Kumar
  Lance Wang, Cadence Design Systems
  Luis Boluna, Cisco Systems
* Michael Mirmak, Intel Corp.
  Mike LaBonte, Cisco Systems
  Mike Steinberger, SiSoft
  Mustansir Fanaswalla, Xilinx
  Patrick O'Halloran, Tiburon Design Automation
  Paul Fernando, NCSU
  Pavani Jella, TI
* Radek Biernacki, Agilent (EESof)
* Randy Wolff, Micron Technology
  Ray Comeau, Cadence Design Systems
  Richard Mellitz, Intel
  Richard Ward, Texas Instruments
  Sam Chitwood, Sigrity
  Sanjeev Gupta, Agilent
  Shangli Wu, Cadence Design Systems
  Sid Singh, Extreme Networks
  Stephen Scearce, Cisco Systems
  Steve Pytel, Ansoft
  Syed Huq, Cisco Systems
  Syed Sadeghi, ST Micro
  Terry Jernberg, Cadence Design Systems
* Todd Westerhoff, SiSoft
  Vikas Gupta, Xilinx
  Vuk Borich, Agilent
* Walter Katz, SiSoft
  Zhen Mu, Cadence Design Systems


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Opens:

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Call for patent disclosure:

- No one declared a patent.


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Review of ARs:

- David Banas report Xilinx position on LTI assumption for SerDes
  - LTI is a good enough assumption for SerDes models

- Arpad:  Write parameter passing syntax proposal (BIRD draft)
          for *-AMS models in IBIS that is consistent with the
          parameter passing syntax of the AMI models
          - TBD

- TBD:    Propose a parameter passing syntax for the SPICE
          - [External ...] also?
          - TBD

- Arpad:  Review the documentation (annotation) in the macro libraries.
          - Deferred until a demand arises or we have nothing else to do

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New Discussion:

Michael M Presentation: Proposal for New Keywords to Improve Buffer Impedance Modeling
- Page 4:
  - This allows for parallel RC circuits in addition to C_comp
  - Improves both time and freq domain modeling.
    - Supports JEDEC DDR Rdie approach
    - JEDEC Rdie is not the same as Rdie as used in power delivery tools
  - Square box at right side is the pad.
- Page 6:
  - Voltage dependence may cause problems for the LTI assumption.
  - David: C_comp will be state dependent.
  - Mike L: Is C_comp different in high and low states?
    - Yes, Arpad published a study on this in his training class.
    - David: Looking at actual data, the H/L difference is smaller than on/off
  - There is no statement here about typ/min/max corner relationships for C_Comp.
  - Bob: Is there a defined method to extract this?
    - Michael M: There are some crude methods
- Page 8:
  - Methods to calculate C_comp:
    - 1: C = I/dVdt
      - Time domain simulation is used for this
      - David: Xilinx gets good results with this method
    - 2: Hazem Hegazy described an LC tuned circuit method
    - 3: AC analysis
      - This is described in the IBIS cookbook
- Page 10:
  - Michael M: We need to allocate C_comp correctly
    - It must be correct in both input and output mode
- Page 11:
  - Proposed fix: adjust V-T tables for total C_comp
- Page 13:
  - C_comp is very Freq dependent, V dependent to a lesser degree
- Page 14:
  - Luca Giacotto and Arpad Muranyi created a model for this
  - Buffer impedance can be modeled with an RC ladder
- Pages 15 & 16:
  - Ladder RC correlation to transistor SPICE much better than single C
- Page 19:
  - Proposal: Create a fixed circuit template with 3 Rs and 3 Cs
  - Good up to 2GHz

- Michael M: We should have a better impedance representation:
  - It must be better than I-V tables
  - It must be better than single C_comp
  - How do we resolve the charge storage problem?
  - How do we resolve state dependence?

Walter: An external interconnect subckt could be used for this
- We would have to allow table driven resistors and capacitors
- Some companies are using S-param models for TX/RX
- The subckt should have ports for driver enable/stimulus
  - This would allow modeling of state dependence
- Todd: We could use an arbitrary subckt instead of creating a fixed structure
- Michael M: It may be tricky to make buffer simulation work with arbitrary circuits
- Arpad: This is a can of worms: an external subckt might have a transistor model
  - Todd: It depends on what elements we allow
- Walter's proposal would still have V-T tables.
  - Waveforms should be stored unprocessed.
  - Michael M: Assume traditional SPICE not used to characterize IBIS data
- Arpad: Clarification: the proposed subckt is in addition to I-V tables
- Michael M: It is important to note that V-T curves have to de-embed C_comp structure
  - Otherwise C_comp will be double counted
- Arpad: One solution is to directly model K factor curves
  - This would bypass the "IBIS kernel" that calculate K factor
- Bob: C_comp structures can be de-embed from waveforms at simulation time
  - Gets around the [Driver Schedule] problem
- Todd: Would this process assume the subckt contents are a black box?
- Michael M: We should try to salvage traditional IBIS extraction methods
- Arpad: If we model K factor directly, we could have done this in the AMS model
  - The model maker will have more work in this case
- Todd: The 7 terminal IBIS buffer is nothing more than an IBIS SPICE element
- Arpad: Then we only need to add RC branches
  - Walter: We would want to have S-param elements too
- Walter: We must clarify that these are not interconnect circuits

We will continue next week

Next meeting: 07 October 2008 12:00pm PT

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